1. Field of Invention
The present invention relates to a signal transmission circuit, a CMOS semiconductor device, and a circuit board, and more particularly, to a signal transmission circuit having an assist-circuit, a CMOS semiconductor device having an assist-circuit, and a circuit board having an assist-circuit.
2. Description of Related Art
As the size of a semiconductor integrated circuit device increases, the size of a semiconductor chip that forms the semiconductor integrated circuit device is also increased. As a result, the length of a signal wire that is formed inside the semiconductor chip (for example, a signal wire for distributing a clock, a signal wire that forms a bus line, or the like) tends to be long.
FIG. 1 shows the configuration of each type of signal wire formed inside an integrated circuit device. A large-scale integrated circuit device is formed inside a square semiconductor chip CP whose side length is approximately 15 mm through 20 mm. Therefore, it is not unusual that the wire length of a signal wire LIN formed inside an integrated circuit device reaches over 20 mm.
A shown in FIG. 1 shows a wiring configuration of a circuit in which the line length of a signal line LIN between a driver circuit DR and a driven circuit RC is less than 100 .mu.m. B shows a wiring configuration of a circuit in which the line length exceeds 20 mm. C shows a wiring configuration of a circuit like a bus line or a clock distribution line in which multiple driven circuits RC are connected to a signal line LIN.
Wiring capacitance CL is generated on a signal line LIN that connects between a driver circuit DR and a driven circuit RC. Input capacitance CG is formed at the input terminal of the driven circuit RC. The values of the wiring capacitance CL in A, B, and C differ from each other, and the values of the input capacitance CG in A, B, and C differ from each other. The value of the input capacitance CG is proportional to the number of driven circuits RC connected to the signal line LIN. The value of the wiring capacitance CL is proportional to the length of the signal line LIN.
Seeing the wiring configurations A, B, and C from this view point, the wiring configuration A, when it is connected to the signal line LIN, has the smallest capacitance value. Subsequently, the capacitance value of the wiring configuration B is larger than that of the wiring configuration A, and the capacitance value of the wiring configuration C is larger than that of the wiring configuration B. Depending on the value of this capacitance, the transmission characteristic of a signal differs greatly.
FIG. 3 shows the wave-forms of step response waves that are generated when a step pulse is supplied to each of these wiring configurations A, B, and C. FIG. 3A shows the wave-form of a step response wave that is generated by the wiring configuration A shown in FIG. 1. FIG. 3B shows the wave-form of a step response wave that is generated by the wiring configuration B shown in FIG. 1. FIG. 3C shows the wave-form of a step response wave that is generated by the wiring configuration C shown in FIG. 1. As is evident from FIG. 3, at the wire length of the wiring configuration A shown in FIG. 1, virtually no delay is visible in the rise of the step wave-form. However, in the wiring configurations B and C, the shapes of the step waves are greatly rounded, generating long response delays. In particular, this tendency appears prominently in the wiring configuration C having a long signal line LIN to which many driven circuits RC are connected.
FIG. 4 shows the wave-forms of response waves. The wiring configuration A transmits an input pulse to the driven circuit RC almost normally. However, the wiring configurations B and C hardly transmit the pulse to their driven circuits RC, respectively. In other words, it can be seen that a signal line having a large capacitive cannot transmit a pulse having a narrow pulse width. This is a main factor inhibiting development of a large-scale semiconductor chip.
The content of this factor also applies as a similar phenomenon to a signal line that connects between integrated circuit devices packaged on a circuit board (printed wiring board).
It should be noted that, in order to increase the degree of integration of a semiconductor integrated circuit device, the processing dimensions of a device such as a transistor need to be fined, and the widths of the wires must be formed thin. In this respect, it can be considered that the value of the capacitance generated on the signal line will become small. However, when the wire width is formed thin, the thickness of the insulation layer is also formed thin at the same time. Consequently, the wiring capacitance CL of the signal line and the input capacitance CG of the driven circuit RC do not decrease by a large amount even if the formation area is decreased as a result of the increased degree of integration.
On the other hand, in order to solve this problem, for example, in a circuit in which a clock pulse is distributed to many circuit regions MAP as shown in FIG. 5, a large capacitance driver circuit DR.sub.1, a medium capacitance driver circuit DR.sub.2, and a small capacitance driver circuit DR.sub.3 can be connected to the circuit, which is seemingly a feasible method. However, if driver circuits DR.sub.1, DR.sub.2, and DR.sub.3 are connected to each signal line LIN, the number of circuits inside the integrated circuit increases. As a result, the amount of power consumption also increases. In addition, the number of circuits for a signal to pass through also increases. Therefore, the timing accuracy also deteriorates.